Manual - Faradaem

Before you start

Faradaem runs a real simulator on your machine. It does not estimate, and it does not ask a model for a number. Every value it reports came out of an ngspice process that ran while you waited.

You are reading the published manual. That page runs ngspice itself, so the next section works there as written, on every circuit including the SKY130 amplifiers. What it cannot do is everything downstream of a measurement — asking for a design, laying one out, running the foundry's deck — and every section marked Local app required below is one of those. Install as described here and all of it works.

On a new machine, run python install.py once. It fetches the two things Faradaem needs and is not, the console build of ngspice and the SKY130 technology files, and unpacks them into ~/.faradaem/tools, where the tool looks for them on its own. Nothing goes on your PATH, nothing needs an environment variable, and nothing is installed with pip. Run python install.py --list first to see the exact URLs, sizes and checksums without fetching anything.

To use builds you already have instead, name them: set FARADAEM_NGSPICE to the full path of your ngspice_con.exe, and PDK_ROOT to the root of your SKY130 install. Both outrank anything the installer wrote. Faradaem never uses ngspice.exe, because that build opens a window and never returns.

The PDK is needed by the four SKY130 circuits, the NFET amplifier, the op-amp, the OTA and the folded cascode, and by every layout check. Every other circuit runs without it, and if the kit is missing only those circuits stop working, and they say what to run.

To see what this machine has and what it lacks, run python doctor.py. It checks everything at once, through the same functions the tool itself uses, and prints the exact fix for anything missing.

Running a simulation

Pick a circuit from the tabs at the top of the form. Set the component values, or click one of the examples to load a worked set. Then press Run simulation, or just press Enter.

Every value field reads numbers the way engineers write them: 10k, 2.2u, 5meg, 4.7 pF and plain 1e-12 all work, with the usual case rule that M is mega and m is milli. The echo beside each label shows what your entry was read as, so a wrong prefix is caught before a simulation is spent on it.

Every measured sizing this session joins a small History row above the form. The arrow chips walk back and forth through them and restore the values into the form; measuring again is your click, because a restore never spends a simulation on its own.

View netlist under the run button shows the exact SPICE deck your values produce, the same text that is handed to ngspice, with only the data-file names replaced by placeholders. It follows your edits live.

The schematic redraws as you type, so the picture always matches the values in the form. Measured numbers behave differently: they appear only after a run finishes, and while a run is in flight the previous reading dims instead of disappearing. Nothing on the page is ever a guess at what the answer might be.

Keyboard

The whole simulator works without a mouse.

Enter: Run the simulation.
Up, Down: Step the value in the focused field. Stepping down out of a decade steps finer, so 1000 goes to 900 rather than to zero.
Shift + Up, Down: Step by a full decade instead.
Left, Right: Move along the circuit tabs when a tab has focus, selecting each one as you reach it. Up and Down do the same. Both wrap: right from the last circuit lands on the first.
Home, End: Jump to the first or last circuit, and select it.
Enter, Space: On a circuit tab, select the focused circuit. The arrows already do this, so these are here for anyone who expects them.
Tab: Reaches the circuit strip once rather than ten times: the selected tab is the strip's single stop, and the arrows move within it.
Ctrl + Enter: Run from anywhere on the page. In the strategist box it sends the message instead, because that is what it means there.
Esc: Dismiss an error message.

Reading the result

Headline: The main measured value for this circuit, in large type. This is a simulator output.
Analytic check: A closed form evaluated separately and shown beside the headline, so you can see whether the two agree.
Badge: Reads agrees when the measurement and the closed form match within tolerance, or off by X% when they do not.
Stats row: Supporting measurements: bandwidth, drain current, power, and so on, depending on the circuit.
Bode plot: Magnitude above phase, plotted against log frequency. Hover anywhere on it to read the exact values at the nearest swept sample.
Schematic tag: The measured value pinned to the output node of the drawing, so the number and the place it was measured stay together.

What the analytic check is, and what it is not

The simulator produces the result. The closed form is only a check on it. When the two disagree, Faradaem shows both and never quietly splits the difference or hides one of them.

The SKY130 circuits, the NFET amplifier, the op-amp and the OTA, deliberately ship no analytic check at all. Square law does not describe a 150 nm short channel device, and its bandwidth is set by the transistor's own output resistance, which no formula in this codebase predicts. A check that was permanently tens of percent out would read as a fault in the simulator rather than as the known limit of the formula. The operating point is shown instead, and that also comes from ngspice.

When a badge says off by some percent

That is not automatically a bug. There are three honest reasons a measurement and a closed form can disagree, and it is worth knowing which one you are looking at.

Real effect: The formula ignores something the simulator does not. Load the Low open-loop gain example on the inverting amplifier: the ideal gain formula assumes infinite open-loop gain, so at A0 = 100 the real closed-loop gain misses it by about 6 percent. The gain times bandwidth product still agrees, which tells you the simulator is right and the formula is incomplete.
Sweep resolution: The sweep runs at 20 points per decade. A very sharp resonance can fall between samples, so a measured peak can be slightly off even though the circuit is fine.
Outside the assumptions: The circuit is operating somewhere the formula was never meant to cover, such as a transistor pushed into triode.

Phase margin, and why it needs the loop opened

Every other measurement here comes from a closed loop response: drive the input, read the output. Phase margin does not live there. It is a property of the loop gain, which is what the signal is multiplied by on one trip around the feedback path, and no amount of looking at the closed loop response recovers it.

So Faradaem opens the loop. The two-pole amplifier netlist contains two copies of the same circuit: one wired normally, and one with the loop cut at the amplifier input and a test signal injected there. Both are swept at once, so the closed loop numbers and the loop gain come from the same run and the same frequency points.

The plot for that circuit shows the loop gain, not the closed loop response, because that is where the headline number is read. Phase margin is how far the phase still is from 180 degrees at the frequency where the loop gain passes 0 dB. Less margin means a peakier, more ringing response, and at zero the circuit oscillates.

Gain margin is deliberately not reported. A two-pole loop approaches 180 degrees of phase shift but never reaches it, so its gain margin is infinite, and any number printed there would be an artifact of where the sweep happened to stop.

Bias warnings on the SKY130 amplifier

A transistor amplifier only works over a range of gate bias. Outside it the numbers stop meaning what you expect, so Faradaem says so rather than printing them without comment.

Bottomed out: The drain has been pulled down near ground and the device is in triode. The gain is far below what the stage can do. Lower Vgs, or lower RD.
Barely conducting: The drain is sitting almost at VDD and the device is close to off. Raise Vgs.
Not amplifying: The device is off. There is no bandwidth to measure, so the run is refused and the message reports the drain voltage and current ngspice actually settled at. Raise Vgs above the threshold, which is around 0.5 V for this device.

The bias on the schematic

The numbers analog engineers pencil beside every transistor, drawn by the tool instead. After a SKY130 circuit measures, Annotate bias (1 simulation) appears under the schematic. One operating-point run reads every device's drain current, transconductance, gate and drain voltages, the saturation voltage the model computed, and the headroom between them, at the exact bias the bench measured. Then hover any transistor: its numbers appear beside it, with the headroom coloured by how much room is left.

The numbers come from the model card through ngspice, never derived. A vector the model does not expose reads "not exposed", and an edited sizing clears the annotations, because they described the old one.

The folded cascode, and why a third topology

The Folded cascode is the third SKY130 amplifier, and the reason it is here is not really the circuit. It is the question a third topology answers: whether the machinery built for the first two generalises, or whether every new circuit costs another round of special cases.

It generalised. Fourteen devices went through the placer, the router, the rule check and the comparison against the netlist without a line of any of them changing, and came out clean on the first attempt.

It also earns its place, which a topology has to. Against the five-transistor OTA it carries about fourteen decibels more gain and better than twice the bandwidth, and it costs about three times the power to do it. That is the trade a folded cascode exists to make: the cascodes build the output resistance, so one stage reaches a gain that would otherwise need two and the compensation two stages drag along.

One thing it is not. The cascode gate references are ideal voltage sources here, where a finished design would generate them on chip from the same reference current; the page marks them external for exactly that reason. Everything else the other amplifiers get, it gets: Design to spec sizes it, the corner suite runs it, and the layout draws it with its five matched pairs around shared centroids.

From a sentence to geometry

Ask for a design takes a plain sentence and drives the tools itself. It picks a topology from the three SKY130 amplifiers and says why, resolves your targets, seeds a starting point, measures it, and iterates against ngspice if anything is missed.

It does not stop there any more. Once a design meets its targets it lays it out: the geometry is drawn, checked against the PDK, compared against the netlist that was simulated, put through the foundry's own runset, and then the specs are measured a second time with the drawn interconnect loading the nets. What comes back is the area, what the wiring cost, and both verdicts.

Every number in that chain came from ngspice or from KLayout. The model chooses, orders and explains; it never supplies a measurement. If the runset did not run, it is told to say so rather than let the fast check stand in for it, and it is told to name the parts of the circuit that are not in the drawing.

The circuits

DC divider: Two resistors, one operating point. Measures the output voltage. The simplest possible check that the simulator path works end to end.
RC low-pass: Measures the 3 dB corner from an AC sweep. Try the two examples that share a corner at different impedances: every number comes back identical, because R and C trade off exactly.
RC high-pass: The same corner measured from the passband down instead of up.
RLC band-pass: Measures resonance, the two 3 dB skirts, and the Q that follows from them. The examples walk Q from 0.1 upward so you can watch the peak sharpen.
Inverting amp: An op-amp macromodel with a single pole. Measures midband gain, closed-loop bandwidth, and their product. This is where gain-bandwidth stops being a formula and becomes something you can watch trade off.
Two-pole amp: An op-amp with two poles instead of one, which is the point at which stability stops being automatic. Measures phase margin from a real loop gain sweep. Walk the examples and watch the margin fall as the second pole moves toward crossover.
NFET amp (SKY130): A common-source amplifier built on a real process, not on ideal parts. Measures gain, bandwidth, drain voltage, drain current, and power. Needs the PDK. The first run after starting the server takes 10 to 30 seconds while the model library loads.
OTA (SKY130): The five-transistor operational transconductance amplifier: an input pair under a mirror load, output taken at the second drain. One stage, so no compensation is needed and the phase margin sits near 90 degrees. It trades gain (around 37 to 43 dB) for simplicity, bandwidth and power. This is the second topology the strategist can choose.
Op-amp (SKY130): A two-stage Miller op-amp built from eight SKY130 transistors: an input pair under a mirror load, then a common-source second stage, compensated by Cc and its zero-nulling resistor Rz. Measures open-loop gain, unity-gain bandwidth, phase margin and power from one sweep. Needs the PDK. This is also the circuit the design iterator sizes for you.
Folded cascode (SKY130): Fourteen SKY130 transistors: the input pair folds its current into two p-channel sources instead of into a load, and what is left flows through cascodes that build the output resistance. One stage, and around 51 dB of it, because the cascodes make the gain rather than a second stage making it. Against the OTA that is about fourteen decibels more gain and better than twice the bandwidth, at about three times the power. The cascode gate references are ideal sources here, where a finished design would generate them on chip. Design to spec sizes it like the others; the one bench it does not carry is rejection and range.

Where the analyses live

The form at the top sets a circuit up: which circuit, what its parts are, and what one run of it measures. Everything that asks a harder question sits below that, in the Analysis section, as a row of tabs: designing to a spec, the step response, rejection and range, the layout, robustness across corners, and the datasheet that collects all of it.

Only the tabs a circuit can answer appear. A resistor divider has none of them; the op-amp and the OTA carry all six, the folded cascode all but rejection and range. One tab is open at a time, and each one that draws something keeps its plot beside its own numbers rather than a column away from them.

Asking for a design in plain language Local app required

The Ask for a design panel at the top of the simulator takes a sentence instead of numbers. Say what you want built and which numbers matter, and a strategist goes to work: it reads the catalogue, picks a circuit, sets targets, generates and simulates a design, and iterates when the measurements fall short.

The strategist is a language model, but it is held to this project's rule: it never produces a circuit value. It drives the same tools you can drive by hand, and everything it reports comes back from ngspice. Its words appear as words; the numbers appear as cards, straight from the tool results, each with a button that loads that design into the form and reruns it so you can verify it yourself.

The page follows the conversation. The first sizing the strategist works on switches the schematic to the circuit under design, and a status line under the log ticks with the simulation count and the worst margin while the search iterates. When the strategist finishes its turn, the last design that met every target is loaded into the form on its own: the schematic redraws from it and the bench measures it again. Candidates in between never touch your form, so a conversation that tried forty of them moves the schematic twice, start and finish. A turn that never met the spec loads nothing, and the cards keep their buttons if you want an intermediate anyway.

If the strategist thinks a target should be relaxed, it does not decide alone. It asks, and the session waits for your reply. And a turn you no longer want can be stopped: the Stop chip ends the search mid-simulation, the conversation survives, and you can redirect it with your next message.

This needs an API key for a model provider. Set FARADAEM_ANTHROPIC_KEY or FARADAEM_OPENAI_KEY with setx, then reload the page. With both set, a picker appears and you can choose the model per conversation. Keys stay on your machine and are read from your user environment.

Designing to a spec

Some circuits carry a Design to spec panel under their input form. On the op-amp it offers the full story in one button: Generate design from specs. Enter your targets, press it, and a starting design is created for you, sized from the targets themselves. That design is measured immediately. If it already meets every target, you are done. If it falls short, the optimizer takes over and iterates the key components until the spec is met, then loads the result and confirms it with one final simulation.

The starting design comes from two simple scaling rules taken from the hand-designed op-amp: the compensation capacitor tracks the load it must drive, and the bias current tracks the power budget. Those rules only pick where the search starts. Nothing they produce is ever shown as a result; every number on the page still comes from a simulation.

Optimize from the values on the page is the second path: it keeps whatever is in the form as the starting point, so you can refine a preset or your own sizing instead.

Every step of that search is a real ngspice simulation. Nothing is predicted from formulas: the optimizer proposes values, the simulator measures them, and the measurements decide the next move. On the SKY130 op-amp each step loads the model library, so expect the search to take minutes rather than seconds. The progress line counts simulations as they finish.

The search stops the moment every target is met, and reports the best point it found if the budget runs out first. Press Apply result to load the winning values into the form; the page then runs one confirming simulation, so the numbers you see are measured, not remembered from the search.

The score beside each step is the worst distance from any target, as a fraction of that target. Zero or better means every goal is met. Leaving the page does not stop a running search; the Stop button does.

Step response: how fast it can actually move

A sweep measures an amplifier held to small signals, where it behaves like the linear model. A step asks a different question: how fast can it move when you stop being polite, and does it stop cleanly when it arrives. Neither answer is visible in a Bode plot.

Run step response on any of the three SKY130 amplifiers rewires the same circuit as a unity-gain buffer, a real closed loop with no servo, and hits it with a 0.3 V step, up and then back down. One transient run, about twenty seconds.

Slew rate is how many volts per microsecond the output manages across the middle of the edge, the tenth to ninetieth percent band, which excludes the corner where it is still linear and the tail where it is recovering. Both edges are measured, because they need not match: a two-stage amplifier charges its compensation capacitor from the tail current on the way up and discharges it through the output stage on the way down. The number reported is the worse of the two, since that is what a datasheet would have to honour, and both are shown underneath.

Settling to 0.1% is when the output last leaves a band that tight around its final value. If it is still moving when the window ends, the answer is that it did not settle in the window, not a number invented to fill the space. Overshoot is how far past the final value it went, as a percentage of the step; a well compensated amplifier with seventy degrees of margin will show almost none.

The window sizes itself from the parts that set the slew, the tail current and the capacitor it has to charge, so a slower design is watched for longer. If the output hits a supply rail during the step it is clipping rather than slewing, and the panel says so instead of reporting numbers measured off a flat line.

Rejection and range: the rest of the datasheet

Gain, bandwidth and phase margin describe the path you want. Two numbers describe the paths you do not: CMRR is how much better the amplifier amplifies a difference between its inputs than something both inputs do together, and PSRR is how much better it amplifies that difference than noise arriving on its own supply. Both are quoted in dB, and bigger is better.

Input range and output swing are the other half. An amplifier only works while its transistors have room to stay in saturation, so there is a band of input voltage where it behaves and rails on either side where it does not. The panel wires the circuit as a buffer, sweeps its input from ground to the supply, and reports where the output actually tracked the input. Tracking means unit slope, not merely agreeing: at the bottom of the sweep the amplifier is off and its output sits at zero, which matches a zero input and means nothing.

An AC analysis excites every source in a netlist at once, so one copy of a circuit cannot be asked three questions and give three separable answers. Run rejection and range puts four identical copies in one deck, gives each a single stimulus, and sweeps them together: one library load, four answers, about half a minute.

These are the numbers that tell the two topologies apart. The two-stage op-amp measures about 76 dB of CMRR and 67 dB of PSRR with 1.24 V of range; the five-transistor OTA measures about 57 dB, 36 dB and 0.91 V. The OTA is simpler and needs no compensation, and it is worse at all three, which is a trade rather than a defect.

Layout: what the sizing costs, and whether it is right

A schematic pretends two things that are not true: that a transistor takes no room, and that a wire is free. The Floorplan tab answers both. It places the devices in a row at the foundry's own minimum diffusion spacing, draws them to scale, and reports the area that placement occupies.

Then it does the part that matters. Each net is routed for real: metal1 runs vertically from each pin, metal2 runs horizontally along the net's own track, and the two are joined only where a via says so. Then the wiring is extracted off those polygons. Area, perimeter and overlap are taken at the constants the PDK states for the plane each piece of metal is on; where one net's metal sits over another's, the capacitance goes between those two nets rather than to ground; and every stub, via and track becomes a resistor, so each drawn pin sits on its own node and reaches its net through the metal that connects it. Then the same measurements run again, so the column of numbers says what the interconnect cost rather than what it was assumed to cost.

Two things are left out on purpose and both are reported rather than dropped. Coupling between two wires lying side by side on one plane is measured and not turned into a capacitance, because the technology file gives it as a value and a distance and does not say what the distance is for. And ground's own resistance is drawn and not simulated, because node 0 is the simulator's reference and cannot be split in two.

The two metal layers are not decoration. On one layer every stub coming down from a high track crosses every track below it, which is a short, and a rule checker cannot see it, because two overlapping rectangles look like one wire. Giving the layers directions is how that is avoided.

The panel then answers two questions, and they are different questions. Design rules asks whether the geometry could be manufactured: thirty-six rules, each read from the PDK's own technology file and each carrying the tag the foundry writes in its own error message. Layout versus schematic asks something no rule check can: whether the drawing is the circuit that was simulated. It walks the shapes, works out what is electrically joined to what using only the geometry, finds every transistor where poly crosses diffusion, and compares the nets that fall out against the netlist ngspice ran.

That second question is the one worth having. Geometry can satisfy every spacing rule in the deck and still connect a gate to the wrong net, and nothing about the picture would look wrong. A missing via is the ordinary version of this: the metal is drawn right over the pin, it looks connected, and it is not.

Every dimension and every capacitance is read out of the PDK's own technology file when the run starts, never remembered here: the minimum poly width, the diffusion overhang each transistor needs, the spacing between devices, and the capacitance of a metal layer per square micron and per micron of edge.

Download GDS writes the placement out in the format every layout tool reads, on the real SKY130 layer numbers, so it can be opened in KLayout or Magic and looked at properly. Each device is the whole stack it takes to be a device: the diffusion, the poly gate crossing it, the implant that declares the diffusion n-type or p-type, a column of contacts down the source and the drain, and the local interconnect those contacts land on. The gate gets a contact too, on a pad above the channel, because poly cannot be contacted where it crosses the diffusion. The n-well the p-channel devices share is drawn behind them, both taps are in it, and the two metal layers and the vias between them are in the file as well.

The rules are read from the same technology file and each carries the tag the foundry uses: widths and spacings for poly, diffusion, local interconnect and both metals; the overhangs that turn two overlapping rectangles into a transistor; the n-well the p-channel devices share; the contacts that reach down to the silicon and the vias that climb back up; and two that are not about dimensions at all, that every well holds a tap and that every tap is contacted. A well with nothing tying it to a voltage floats, and a floating well is how a CMOS circuit latches up and destroys itself. The panel says how many rules were checked as well as what passed, because a clean result means nothing without knowing how much was looked at.

Those thirty-six rules are the fast loop, not the answer. The answer is the SKY130 runset, sixteen hundred lines of it, which ships inside the PDK and which KLayout runs over the same GDS. Faradaem hands the file over and reads back what came out; it reimplements nothing.

The difference is not academic. The first time the runset ran, it failed geometry the fast checker had called clean, on forty counts across three rules. All three were the same kind of thing: a via needs more metal along one axis than it needs all round, and the fast checker had implemented the all-round half and stopped. Those three are in it now, because an inner loop that misses what the outer one catches is an inner loop nobody can trust. But the reason anyone knows is that something else looked.

Layout versus schematic runs twice, and the second run is the real one. Faradaem's own comparison pairs devices by their position in the row and checks connectivity; it is fast and it is honest about being no more than that. KLayout's engine is then told what the layers mean and nothing else: it recognises the devices from the geometry, measures widths, lengths, resistances and capacitances off the drawn shapes, and matches the result against the circuit by topology, the way sign-off LVS matches. The drawn resistor comes back at 2000.3 ohms and the capacitor at two picofarads with nothing telling the engine what to expect.

The compensation network is drawn, not idealised: the nulling resistor as poly sized off the PDK's sheet resistance, the Miller capacitor as a metal2 over metal1 plate sized off the PDK's overlap constant. Two picofarads of plate is fifteen thousand square microns, larger than every transistor put together, which is the honest cost of a capacitor on the two metals this stack has. Drawing it cost 3.4 degrees of phase margin, measured. What stays outside the cell is the bias, the load, and for the folded cascode the two ideal gate references, and the panel names them and says which of those is a port and which is a cheat.

The wires are priced in ohms as well as farads: KLayout's square-counting extractor measures each net's worst pin-to-pin path over the drawn rectangles, and the sheet and via values come out of the PDK. On the op-amp the longest wire is the compensation node at 250 ohms, because its track runs 373 microns to reach the far tab of the capacitor.

The devices are also grouped by type, NMOS then PMOS, which is not cosmetic: two separate wells have to stay 1.27 microns apart, and PMOS scattered through the row would put two of them 1.18 apart. Grouped, they share one well.

It is a real layout. The wires are routed on two metal layers and their resistance and capacitance are extracted and priced in margin. Matched pairs are folded into fingers around a shared centroid with dummies at the ends, each group wears a tied guard ring, and every net is a named port in the exported GDS. Layout versus schematic runs through KLayout's own engine, and the foundry's sign-off deck is one button away. What is still simplified is the router itself: one track per net, which is legal and checked, not what a person would draw.

Robustness: corners and Monte Carlo

One passing simulation shows a circuit works at the typical process, room temperature and a nominal supply. The Robustness panel on the SKY130 circuits asks the harder questions.

Run PVT corners reruns the circuit eleven times: the five process corners at nominal conditions, the four supply and temperature extremes, and the two classic cross corners, slow at low supply and hot, fast at high supply and cold. The table shows every condition's measurements and the worst case per metric, with the condition that caused it named. A corner where the circuit cannot be measured is reported as its own finding.

Run Monte Carlo draws twenty mismatch samples using the PDK's statistical models at the typical corner, each under a different seed, and reports the mean, sigma, minimum and maximum per metric. This is what tells you whether a design survives the fact that no two transistors are identical.

The strategist uses the same corner suite: once a design meets its targets at the typical corner, it verifies across PVT and reports the worst case.

Long runs report back. The progress line carries a time estimate from the run's own measured pace, both suites can be stopped mid-run, the corner autopsy included, and the first time a long job starts the browser asks once whether it may notify you; after that, a job that finishes while you are in another tab says so from the notification tray.

The datasheet that writes itself

Engineers lose days assembling characterization reports: the gain from one run, the corners from another, the layout verdicts from a third, pasted into a document that is stale before it is finished. Everything in that document is something this tool already measures, so the Datasheet tab measures it all in one pass and writes the document itself.

The printable page reads as a design review, not a data dump: the verdict sentence first, then the schematic drawn from the stored sizing with its measured tag, then the sizing with units, the targets with the binding one marked, the characteristics with the worst observed corner, and the drawn circuit's verdicts. One button, one page, ready for the meeting.

The button states its cost before you press it, and after the run it reports the count that was actually observed at the simulator boundary, which is the only place simulations are ever counted here. The document that appears carries the sizing it measured, the margins against the circuit's own targets, an electrical characteristics table, and the layout verdicts, headed by a provenance line: the git commit, the simulator version and the PDK the numbers came out of. A number without provenance is an anecdote.

Two honesty rules are visible in the table. The extremes column is titled worst observed, not min or max, because eleven deterministic corner simulations are a sample, not a guarantee; the note under the table says exactly how many corners measured and names any that did not bias. And if you edit a value after characterizing, a banner says the datasheet no longer describes the circuit on the bench. The check is exact on purpose.

Every characterization is stored beside the ledger and listed under the button, newest first. Open renders it in place; Print view opens a black-on-white page built for the printer, so your browser's print-to-PDF produces the document you would hand a reviewer.

Pinned numbers

Software engineers pin behaviour in tests and a machine tells them when it drifts. Analog engineers diff waveforms by eye. The pin gives a circuit the same deal: after a successful run, the result strip offers Pin these numbers. The pin re-measures the sizing on the server and freezes the sizing and the numbers together, so what is pinned is what ngspice said, never what the page happened to hold.

The semantics are deliberately narrow. A check re-simulates the pinned sizing, never the values in the form. Editing an input can therefore never fail a check: drift means the stack moved under the circuit, a model library update, a simulator upgrade, an edit to a bench deck. That is what the feature watches for, and it is why each check records the stack it ran on. The history renders as a row of marks in the Datasheet tab, the first breaking check outlined, and history never crosses a re-pin, because a trend stitched across two different pins would be an invention.

Comparing two runs

A design review is two hours of "wait, which version is this?" The compare section in the Datasheet tab puts side A and side B in one table: every number both carry, with the difference in the third column. Side A defaults to the current sizing measured fresh, one simulation; side B is any stored characterization. When both sides carry corner data the table extends corner by corner.

For the faster loop there is Hold as design A, next to the pin button after any measurement. Hold the design, keep turning knobs, and every later measurement renders the delta table right under the result: each knob and each measured number, A against B, with the change in percent. On the frequency plot, A's response stays under the live curve as a faint trace, so the move you just made is visible as two lines rather than remembered as two numbers.

Rows only one side measured show a dash, and a bench-only side says so in as many words. If the two runs were measured by different simulator versions, PDKs or commits, a warning says to treat cross-run deltas with care, because two stacks are two experiments.

A design as one file

"Send me your setup" answered with a file. Export design, under the run button, writes one JSON file carrying the circuit, the sizing, what it measured here, and which app version wrote it. Import design reads one back on any machine running Faradaem: the right circuit is selected, the sizing lands in the form, and one simulation measures it again on the spot, because the numbers a design shows must come from the simulator in front of you, never from the sender's.

Diagnosing a sizing: triage, blame, the sweep

Under the design goals live three questions, each answered by measurement and nothing else.

Is this spec possible here? is one simulation: every goal gets its margin at the current sizing, and the sentence names the one that binds. It says "at this sizing" and means it; one point at the typical corner proves nothing about the rest of the design space, and the sentence never claims otherwise.

Explain the margins is the question every junior engineer carries to a senior one: which knob moves the number that is failing. The tool measures the answer instead of intuiting it: each tunable is stepped five percent down and up, two simulations per knob, and the table reports how much every goal moved per natural unit of that knob, sorted by effect on the binding goal. The method line under the table says exactly what these are: central differences at this sizing, local slopes, not a model. Extrapolating a five percent secant to a fifty percent move is on you.

Sweep the bias traces the trade the bias current buys: eight simulations along its declared range, plotted as power against crossover. The caption is precise about what this is: a one-knob slice with everything else frozen, not a Pareto front. A real front would need an optimization per point. A point where the amplifier stopped biasing is reported, not dropped, because omitting it would make the reachable range look wider than it is.

The corner autopsy

A corner fails and the traditional next move is an afternoon in a waveform viewer. The autopsy asks the short question directly: which transistor gave up. After any corner suite run, Explain the corners re-runs the eleven conditions with the operating point captured, and tabulates every device's saturation headroom at every corner, in millivolts, negative in red.

Headroom is vds minus vdsat for an n-channel device and the sign-aware mirror for a p-channel one, both read from the foundry's own model card through ngspice at each corner's real operating point. The sentence above the table names the tightest device even when everything holds, because knowing the closest call is worth eleven simulations before tapeout, not after. A device whose model does not expose the number says "not exposed"; it is never shown as zero, and never as fine.

The tapeout packet Local app required

A foundry, a collaborator or a shuttle wants the same short list: the GDS, the netlist it was verified against, the verdicts, and a README saying what everything is. Assembling that by hand is error-prone in exactly the way that ruins tapeouts: a clean report from Tuesday zipped next to Wednesday's GDS.

So the packet button refuses to assemble. It builds: one click renders the geometry, runs the foundry's own deck over those shapes, runs layout-versus-schematic at the same sizing, and only if both pass does a zip exist. The README records the SHA-256 of the GDS it describes, so the binding between the drawing and its verdicts is checkable by anyone holding the file. A failing verdict produces a refusal that names the failure, never a partial packet.

The notebook

Everything this machine measures is recorded as it happens: one ledger file per run, one line per event, the provenance stamped at the head. The notebook page renders that record as the lab notebook engineers mean to keep and do not: every run, its circuits, its simulation count as observed at the simulator boundary, its verdicts, newest first, with older pages a click away.

A damaged line count above zero is shown, never hidden: a truncated record is what a crash leaves behind, and the notebook is exactly where that fact belongs. The stored datasheets live here too, and the whole visible view exports as Markdown for pasting into a report.

The doctor Local app required

Setting up ngspice, a PDK and KLayout on Windows is the worst afternoon of the project, and the errors arrive one at a time, each after a failed run. The doctor runs every check at once:

python doctor.py

Each line is one dependency, resolved through the same functions the tool itself uses, so a green check is the tool's own opinion. A missing one prints the exact fix. Optional pieces -- the strategist's API keys -- report as absent rather than failed, because absent and broken are different facts. The exit code is the number of missing checks, so the doctor also works in a script.

If something goes wrong

Could not reach the Faradaem server: The page loaded but the server is not answering. Start it with python desktop.py, or python server.py if you would rather have a tab, and run again.
Could not locate ngspice: The message lists every place it looked. Run python install.py to fetch one, or set FARADAEM_NGSPICE to the full path of an ngspice_con.exe you already have.
Could not find the SKY130 model library: Only the SKY130 circuits and the layout checks need this. Run python install.py to fetch it, or set PDK_ROOT to the folder holding a kit you already have, then restart the server so it picks up the new value.
A value is refused before the run: Every parameter has a declared range, and the message names the limit it crossed. The form marks the field and says what to do.
The first SKY130 run is slow: That is the model library loading, and it is expected. Later runs on the same circuit are much faster.